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CXD1910AQ
Digital Video Encoder
Description The CXD1910AQ is a digital video encoder designed for set top box, digital VCRs and other digital video applications. The device accepts ITUR601 compatible Y, Cb, Cr data, and the data are encoded to analog composite video and Y/C video (S-Video) signal. Features * NTSC and PAL encoding mode * Composite video and separate Y/C video (SVideo) outputs * Y, U, and V outputs * 8/16-bit pixel data input mode * 13.5 Mpps pixel rate * 10-bit 3 channels DACs * Supports I2C bus (400kHz) and SONY SIO * Closed Caption (Line 21, Line 284) encoding * Macrovision Pay-Per-View copy protection system Rev. 6.1 * Monolithic CMOS single 5.0V power supply * 64-pin plastic QFP package This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anticopy process in the device is licensed by Macrovision for non-commercial home use only. Reverse engineering or disassembly is prohibited. 64 pin QFP (Plastic)
Absolute Maximum Ratings -0.3 to +7.0 * Supply voltage VDD * Input voltage VI -0.3 to +7.0 * Output voltage VO -0.3 to +7.0 * Operating temperature Topr -20 to +75 * Storage temperature Tstg -40 to +125 (Vss = 0V) Recommended Operating Conditions * Supply voltage VDD 4.75 to 5.25 * Input voltage VIN * Operating temperature Topr I/O Capacitance * Input pin * Output pin Vss to VDD 0 to +70
V V V C C
V V C
CI CO
11 (Max.) 11 (Max.)
pF pF
Note) Test conditions: VDD = VI = 0V fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E95235A66-ST
Block Diagram
XRST 55 25 VB
PD0 to 7 Y Delay 10bit DAC
1 to 4, 6 to 9
29 Y-OUT/Y
PD8 to 15 11 to 18 LPF Modulator V LPF
CHROMA
U
Dempx, level translator and interpolator 4:2:2 to 4:4:4 Y, C/ Y, U, V selector and interpolator 10bit DAC
24 COMP-O/V
PDCLK 57
1/2
10bit DAC
32 C-OUT/U
SYSCLK 56 BURST FLAG CSYNC SYNC slope gen. Sub carrier gen. 20 IREF 21 VREF 26 VG
-2-
Closed caption encoder (for NTSC) MACRO VISION signal gen.
VSYNC 59
HSYNC 60
FID 62
SYNC gen. and timing controller
XVRST 51
F1 52
SI/SDA 48
46 TDO 43 TDI 44 TMS 45 TCK 41 TRST
SCK/SCL 49
SIO and I2C-Bus controller
XCS/SA 50
XIICEN 64
37 to 39, 54
XTEST1 to 4 CXD1910AQ
CXD1910AQ
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Symbol PD7 PD6 PD5 PD4 VSS PD3 PD2 PD1 PD0 VDD PD15/TD7 PD14/TD6 PD13/TD5 PD12/TD4 PD11/TD3 PD10/TD2 PD9/TD1 PD8/TD0 VSS IREF VREF AVDD1 AVSS1 I/O I I I I -- I I I I -- I/O I/O I/O I/O I/O I/O I/O I/O -- O I -- -- Digital ground The reference current output pin. Connect resistance "16R" which is 16 times output resistance "R". The voltage reference input pin. Sets output full scale value. Analog power supply Analog ground This is the output of 10-bit D/A converter. When control register bit "YC/YUV" = "1": This pin outputs composite signal. When control register bit "YC/YUV" = "0": This pin outputs color difference (V) signal. Connect to VSS with a capacitor of approximately 0.1F. Connect to AVDD with a capacitor of approximately 0.1F. Analog power supply Analog ground This is the output of 10-bit D/A converter. This pin outputs luminance (Y) signal. 8-bit pixel data input pins / Test data bus. When control register bit "PIF MODE" = "0": These inputs are not used. When control register bit "PIF MODE" = "1": These are inputs for multiplexed Cb and Cr signal. When test mode, it's used for internal circuit test data bus. Test mode is available only for device bender. Description 8-bit pixel data input pins (PD0 to 7). When control register bit "PIF MODE" = "0": These are inputs for multiplexed Y, Cb, and Cr signal. When control register bit "PIF MODE" = "1": These are inputs for Y signal. Digital ground 8-bit pixel data input pins (PD0 to 7). When control register bit "PIF MODE" = "0": These are inputs for multiplexed Y, Cb, and Cr signal. When control register bit "PIF MODE" = "1" These are inputs for Y signal. Digital power supply
24
COMP-O/V
O
25 26 27 28 29
VB VG AVDD2 AVSS2 Y-OUT/Y
O I -- -- O
-3-
CXD1910AQ
Pin No. 30 31
Symbol AVDD3 AVSS3
I/O -- -- Analog power supply Analog ground
Description
32
C-OUT/U
O
This is the output of 10-bit D/A converter. When control register bit "YC/YUV" = "1": This pin outputs chroma (C) signal. When control register bit "YC/YUV" = "0": This pin outputs color difference (U) signal. Test data bus. This pin should be open. When test mode, it's used for internal circuit test data bus. Test mode is available only for device bender. Digital power supply Test data bus. These pins should be open. When test mode, it's used for internal circuit test data bus. Test mode is available only for device bender. Test mode control input pins. These pins are pulled up. When these pins are "H", the CXD1910AQ is not test mode. Test mode is available only for device bender. Digital ground Test mode reset input pins. When power on reset, set "L" for more than 40 clocks (SYSCLK). Digital power supply Test mode control input pins. This pin is pulled up. Test mode control input pins. This pin is pulled up. Test mode control input pins. This pin should be "H" input. Test data bus. This pin should be open. Digital ground This pin's function is selected by XIICEN (Pin 64). When XIICEN = "H", this pin is SONY SIO mode; SI serial data input. When XIICEN = "L", this pin is I2C-BUS mode; SDA input/output. This pin's function is selected by XIICEN (Pin 64). When XIICEN = "H", this pin is SONY SIO mode; SCK serial clock input. When XIICEN = "L", this pin is I2C-BUS mode; SCL input. This pin's function is selected by XIICEN (Pin 64). When XIICEN = "H", this pin is SONY SIO mode; XCS chip select input. When XIICEN = "L", this pin is I2C-BUS mode; SA slave address select input signal which selects I2C-BUS slave address. Vertical sync reset input pin in active low. This pin is pulled up. This is used to synchronize external vertical sync and internal vertical sync. When XVRST is "L", internal digital sync generator is reset according to F1 status.
33
TD10
I/O
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
VDD TD9 TD8 XTEST1 XTEST2 XTEST3 VSS TRST VDD TDI TMS TCK TDO VSS SI/SDA
-- I/O I/O I I I -- I -- I I I O -- I
49
SCK/SCL
I
50
XCS/SA
I
51
XVRST
I
-4-
CXD1910AQ
Pin No.
Symbol
I/O
Function Field ID input. For external synchronization with XVRST signal, the field for resetting is determined by the main signal. "H" indicates 1st field. "L" indicates 2nd field. Digital power supply Test mode control input pin. This pin is pulled up. When this pin is "H", the CXD1910AQ is not test mode. Test mode is available only for device bender. System reset input pin in active low. When power on reset, set "L" for more than 40 clocks (SYSCLK). System clock input pin. To generate correct subcarrier frequency, precise 27MHz is required. Pixel data clock output pin for 13.5MHz. This clock is divided from SYSCLK. This is used when 16-bit pixel data mode. Digital ground Vertical sync signal output pin. Horizontal sync signal output pin. This pin's function is selected by XIICEN (Pin 64). When XIICEN = "H", this pin is SONY SIO mode; SO serial out output pin. When XIICEN = "L", this pin is not used and output is high impedance. Field ID output pin. When control register bit "FIDS" = "1": "L" indicates 1st field, "H" indicates 2nd field. When control register bit "FIDS" = "0": "H" indicates 1st field, "L" indicates 2nd field. Digital power supply Serial interface mode select input pin. This pin is pulled up. When XIICEN = "L", Pins 48 to 50 and 61 are I2C-BUS mode. When XIICEN = "H", Pins 48 to 50 and 61 are SONY SIO mode.
52
F1
I
53 54
VDD XTEST4
-- I
55 56
XRST SYSCLK
I I
57 58 59 60 61
PDCLK VSS VSYNC HSYNC SO
O -- O O O
62
FID
O
63 64
VDD XIICEN
-- I
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CXD1910AQ
Electrical Characteristics DC characteristics Item Input high voltage Input low voltage Output high voltage Output low voltage Output high voltage Output low voltage Input leak current Input leak current Supply current Symbol VIH VIL VOH1 VOL1 VOH2 VOL2 II1 II2 IDD Conditions VDD = 5.0V 5% VDD = 5.0V 5% IOH = -2.4mA VDD =4.75 to 5.25V IOL = 4.8mA VDD = 4.75 to 5.25V IOH = -1.2mA VDD = 4.75 to 5.25V IOL = 2.4mA VDD = 4.75 to 5.25V VI = 0 to 5.25V VDD = 4.75 to 5.25V VI = 0V VDD = 5.0V 5% VDD = 5.0V 5% -10 -40 -100 VDD-0.8 0.4 10 -240 706 VDD-0.8 0.4 Min. 2.2 0.8 Typ. (Ta = 0 to +70C, Vss = 0V) Max. Unit V V V V V V A A mA Pins 1 1 2 2 3 3 4 5
1 PD0 to 15, TD8 to 10, XTEST1 to 4, TRST, TDI, TCK, SI/SDA, SCK/SCL, XCS/SA, XVRST, F1, XRST, SYSCLK, XIICEN 2 PDCLK, VSYNC, HSYNC, FID, SO 3 TDO, TD0 to 10 4 PD0 to 15, TD8 to 10, TCK, SI/SDA, SCK/SCL, F1, XRST, SYSCLK 5 XTEST1 to 4, TRST, TDI, TMS, XCS/SA, XVRST, XIICEN 6 Not include analog supply current
DAC characteristics 1 Item Resolution Linearity error Differential linearity error Output full-scale current Output offset voltage Output full-scale voltage Precision guaranteed output voltage range Symbol n EL ED IFS VOS VFS VOC
(AVDD = 5V, R = 200, VREF = 1.35V, Ta = 25C) Measurement conditions Min. Typ. 10 -2.5 -1.5 6.25 6.75 2.5 1.5 7.25 1 1.25 1.25 1.35 1.35 1.45 1.45 Max. Unit bit LSB LSB mA mV V V
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CXD1910AQ
DAC characteristics 2 Item Resolution Linearity error Differential linearity error Output full-scale current Output offset voltage Output full-scale voltage Precision guaranteed output voltage range Symbol n EL ED IFS VOS VFS VOC
(AVDD = 5V, R = 200, VREF = 2.0V, Ta = 25C) Measurement conditions Min. Typ. 10 -2.0 -1.0 9.5 10.0 2.0 1.0 10.5 1 1.9 1.9 2.0 2.0 2.1 2.1 Max. Unit bit LSB LSB mA mV V V
AC characteristics 1. Pixel Data Interface (1) 8-bit mode
SYSCLK tPDS tPDH
PD0 to 7
(Ta = 0 to +70C, VDD = 4.25 to 5.25V, Vss = 0V) Item Pixel data setup time to SYSCLK Pixel data hold time to SYSCLK Symbol Min. 10 3 Typ. Max. Unit ns ns
tPDS tPDH
(2) 16-bit mode
PDCLK tPDS tPDH
PD0 to 15
(Ta = 0 to +70C, VDD = 4.75 to 5.25V, Vss = 0V) Item Pixel data setup time to PDCLK Pixel data hold time to PDCLK Symbol Min. 20 0 Typ. Max. Unit ns ns
tPDS tPDH
-7-
CXD1910AQ
2. Serial Port Interface
fSCK tPWLSCK SCK tCSS XCS tSIS SI tSOD SO tSOH tSIH tCSH tPWHSCK
(Ta = 0 to +70C, VDD = 4.75 to 5.25V, Vss = 0V) Item SCK clock rate SCK pulse width Low SCK pulse width High Chip select setup time to SCK Chip select hold time to SCK Serial input setup time to SCK Serial input hold time to SCK Serial output delay time from SCK Serial output hold time from SCK Symbol fSCK Min. DC 100 100 150 150 50 10 30 3 Typ. Max. 3 Unit MHz ns ns ns ns ns ns ns ns
tPWLSCK tPWHSCK tCSS tCSH tSIS tSIH tSOD tSOH
3. XVRST, F1
PDCLK tVS tVH
XVRST F1
(Ta = 0 to +70C, VDD = 4.75 to 5.25V, Vss = 0V) Item XVRST, F1 setup time to PDCLK XVRST, F1 hold time to PDCLK Symbol Min. 20 0 Typ. Max. Unit ns ns
tVS tVH
-8-
CXD1910AQ
4. SYSCLK, PDCLK, VSYNC, HSYNC, FID
fSYSCLK tPWHCLK tPWLCLK
SYSCLK tPDCLKD
tPDCLKD PDCLK
tOD tOH
VSYNC, HSYNC, FID
(Ta = 0 to +70C, VDD = 4.75 to 5.25V, Vss = 0V) Item SYSCLK clock rate SYSCLK pulse width Low SYSCLK pulse width High PDCLK delay time from SYSCLK Control output delay time from SYSCLK Control output hold time from SYSCLK Symbol fSYSCLK Min. Typ. 27 11 11 20 25 3 Max. Unit MHz ns ns ns ns ns
tPWLCLK tPWHCLK tPDCLKD tCOD tCOH
-9-
CXD1910AQ
Description of Functions The CXD1910AQ converts digital parallel data (ITU-R601 Y, Cb, Cr) into analog TV signals in NTSC (RS170A) or PAL (ITU-R624; B, G, H, I) format. The CXD1910AQ first receives image data in 8-bit parallel form (multiplexed Y, Cb, and Cr data), or in 16-bit parallel form (8-bit Y and 8-bit multiplexed Cb and Cr data). After demultiplexing, it converts Cb and Cr signals into U and V signals respectively, interpolates 4:2:2 to 4:4:4, and modulates the signals with the subcarrier generated by digital subcarrier generator. Y signal and modulated chroma signal are oversampled (at double) to reduce sin (x)/(x) rolloff. 10-bit DACs are used for converting digital composite and Y/C signals into analog signals. 1. Pixel Input Format Pixel input format is determined by bit 4 (PIF MODE) of control register address 01H, as shown in Table 1-1. When PIF MODE is "0", the image data (Y, Cb, Cr) input from PD0 to PD7 is sampled at the rising edge of SYSCLK. When PIF MODE is "1", Y data is input into PD0 to 7, multiplexed Cb and Cr data are input into PD8 to 15, and these respective data are sampled at the rising edge of PDCLK. PIF MODE 0 (8-bit mode) 1 (16-bit mode) PD15 to 8 NA Cb/Cr Table 1-1 PD7 to 0 Y/Cb/Cr Y
Pixel Data Input Timing
SYSCLK PDCLK HSYNC
[16-bit mode] PD0 to 7 PD8 to 5 [8-bit mode] PD0 to 7 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 Cr4 Y5 Cb6 Y0 Cb0 Y1 Cr0 Y2 Cb2 Y3 Cr2 Y4 Cb4 Y5 Cr4
PD0 PD1 : PD7
Pixel data 0 (LSB) Pixel data 1 : Pixel data 7 (MSB)
PD8 PD9 : PD15
Pixel data 0 (LSB) Pixel data 1 : Pixel data 7 (MSB)
- 10 -
CXD1910AQ
2. Serial Interface The CXD1910AQ supports both I2C-BUS (high-speed mode) and SONY's serial interface. These modes can be selected by XIICEN input pin as shown in Table 2-1 below. XIICEN SI/SDA SCK/SCL XCS/SA SO H SONY SIO mode SI SCK XCS SO Table 2-1 I2C L mode
SDA SCL SA High-Z
2-1. I2C-BUS interface The CXD1910AQ becomes a slave transceiver of I2C-BUS, and supports the 7-bit slave address and the highspeed mode (400K bit/s). 2-1-1. Slave address Two kinds of slave address (88H, 8CH) are selectable by the SA signal, as shown in Table 2-2 below. A6 1 A5 0 A4 0 A3 0 A2 1 A1 SA A0 0 R/W X
Table 2-2
2-1-2. Write cycle S slave address W "0" from master to slave from slave to master A start address A write data A write data A P
D7 start address
D6
D5
D4
D3
D2
D1
D0
ADR [4 : 0]
After the slave address is supplied from the master, the data in the next transfer cycle is set up inside the start address register of this IC as start address of the control register. In subsequent cycles, the data supplied from the master is written in the addresses indicated by the control register address. The set control register address is automatically incremented with the completed transfer of each byte of data.
- 11 -
CXD1910AQ
2-1-3. Read cycle
S
slave address
R "1"
A
read data
A
read data
A
P
from master to slave from slave to master
After the slave address is supplied from the master, subsequent cycles change immediately to read cycles and only ID code (address 09H, 0AH) is read out. During the read cycle, the start address is automatically set to 09H. Note) In the SONY SIO mode, addresses from 00H to 0AH can be read out. 2-1-4. Handling of general call address (00H) General call address is neglected and there is no ACK response.
- 12 -
CXD1910AQ
2-2. SONY serial interface SONY serial interface uses SCK, XCS, SI and SO signals. Serial interface is activated when XCS signal is "Low", and samples serial input data at the rising edge of SCK. The first one byte after XCS activation is set up as a serial control command. The data includes a start control register address and direction of the serial interface. The control register address is automatically incremented with the transfer of each byte of data. In the write mode, the data of second byte and after are written in the addresses indicated by the address generated by the address generator of the CXD1910AQ. In the read mode, the serial input data is neglected and writing is not done. Serial Interface Timing
SCK XCS SI D0 LSB SO D1 D2 D3 D4 D5 D6 D7 MSB D0 LSB D0 D1 D2 D1 D2 D3 D4 D5 D6 D7 MSB D5 D6 D7
Serial control command
Serial data D3 D4
Serial Interface Sequence
SCK XCS SI Internl address generator 00H FFH 00H 11H 01H CEH 02H
Start control register address set Control register address auto-increment Control register address 00H 01H 02H Control register data FFH 11H CEH
Control register address auto-increment
2-1. Serial control command format D7 WR WR D6 D5 D4 D3 D2 D1 D0
ADR [4 : 0] : Direction for serial interface When this bit is "1": The serial interface is write mode. Incoming serial data is set up inside the control register according to the control register address. When this bit is "0": The serial interface is read mode. The control register data is output to SO according to the control register address.
ADR [4 : 0] : Start control register address - 13 -
CXD1910AQ
3. XVRST, F1 XVRST and F1 signals are used to synchronize with external V. sync. XVRST and F1 signals are sampled at the rising edge of PDCLK, and F1 signal is sampled when XVRST is Low. When F1 is High, the internal sync generator is reset to the 1st field, and when F1 is Low, it is reset to the 2nd field. When XVRST is set at High, digital sync generator starts operation, and the sequence of 1st or 2nd field starts. XVRST Timing (1st Field)
PDCLK
XVRST
F1 "H" VSYNC F-ID HSYNC
Start of 1st field (NTSC : 4H) (PAL : 1H)
XVRST Timing (2nd Field)
PDCLK
XVRST
F1 "L" Start of 2nd field (NTSC : 266H) (PAL : 313H) VSYNC F-ID 1/2H HSYNC
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CXD1910AQ
4. Closed Caption The CXD1910AQ supports closed caption encoding. ASCII data for closed caption encodes line 21 and line 284 by adding parity bit to ASCII data (data #1 and data #2 for line 21, data #1 and data #2 for line 284) which is set up for control registers 03H, 04H, 05H and 06H. Control registers 03H to 06H are double-buffered and ASCII data which is set up by serial interface is synchronized with VSYNC. Double Buffer for Closed Caption
SI/SDA
03H
VSYNC
Load
ASCII data #1
Closed Caption Data Renewal Timing
VSYNC Set control register 03H SI/SDA NEW DATA
Data#1
OLD DATA
NEW DATA
Closed Caption Signal Waveform
HSYNC Color burst Clock run-in Start bits ASCII data#1 ASCII data#2
S1 S2 S3 b0 b1 b2 b3 b4 b5 b6 P1 b0 b1 b2 b3 b4 b5 b6 P2
50 IRE
- 15 -
NTSC Vertical Interval
Fields 1and 3 Vertical blanking
Preequalization 3H Vertical SYNC 3H Postequalization 3H
524 20
525
1
2
3
4
5
6
7
8
9
10
11
19
21
22
23
HSYNC
VSYNC
- 16 -
264 265 266 267 268 269 270 271 272 273 274
FID
Fields 2 and 4
261
262
263
282
283
284
285
HSYNC
VSYNC
FID CXD1910AQ
PAL Vertical Interval
Fields 1and 3
2.5H
2.5H
2.5H
620 21
621
622 624 625 1 2 3 4 5 6 7 8 20 22
623
23
24
HSYNC
VSYNC
FID
- 17 -
Fields 2 and 4 312 313 314 315 316 317 318 319 320 321
308
309
310
311
333
334
335
336
HSYNC
VSYNC
FID CXD1910AQ
CXD1910AQ
Vertical Synchronization Timing
0.148s 0.148s
2.3s
29.5s
27.1s 1/2H 63.555s
4.67s
NTSC Equalizing & Synchronizing Pulses
0.296s
0.296s
2.37s
29.63s
27.3s 1/2H 64s
4.67s
PAL Equalizing & Synchronizing Pulses
- 18 -
CXD1910AQ
Control Register Map Note) For the bit which is not assigned, use it by setting "0". BIT Function Selection #1 7 Address 00H FIDS ENC MODE 6 MASK EN 5 PIX EN 4 YC/YUV 3 BF 2 SET UP 1 0 ENC MODE R/W
Encoding mode 0 : PAL encoding mode 1 : NTSC encoding mode (Default) Set up enable 0 : Non set up level, black = blanking level 1 : 7.5 IRE set up level insertion (Default) Burst flag enable 0 : Disable burst flag 1 : Enable burst flag (Default) Color burst exists or not can be selected.
SET UP
BF
YC/YUV
DAC output function select 0 : Y, U, V output mode 1 : Video signal (Comp, Y, C) output mode (Default) Pixel data enable 0 : Disable input pixel data 1 : Enable input pixel data (Default) When input pixel data is disabled, output becomes blanking level or black level regardless of input PD0 to PD15.
PIX EN
MASK EN
Mask enable 0 : When V-blanking, pixel data through 1 : When V-blanking, pixel data reject (Default) When MASK EN = "0", input pixel data during V-blanking interval are valid, and output obeys input pixel data. When MASK EN = "1", input pixel data during V-blanking interval are all invalid, and output becomes blanking level. As for this mode, input pixel data under 16 (0 to 16) is limited to 16; input pixel data more than 235 (235 to 255) is limited to 235.
FIDS
FID polarity select 0 : 1st field "H", 2nd field "L" 1 : 1st field "L", 2nd field "H" (Default) - 19 -
CXD1910AQ
BIT Function Selection #2 7 Address 01H 6 5 4 PIF MODE Pixel input format 0 : 8-bit mode Multiplexed Y, Cb, Cr (4:2:2) (Default) 1 : 16-bit mode Y and multiplexed Cb, Cr DAC output activity 0 0 : Non-active 0 1 : Y-OUT and C-OUT active 1 0 : Comp-out active 1 1 : Both active (Default) 3 2 1 0 R/W
DAC MODE
PIF MODE
DAC MODE
BIT Function Selection #3 7 Address 02H CC MODE 6 5 4 3 ZERO 2 1 0 R/W
CC MODE
Closed caption encoding mode 0 0 : Disable closed caption encoding (Default) 0 1 : Enable encoding in 1st field (Line 21) 1 0 : Enable encoding in 2nd field (Line 284) 1 1 : Enable encoding in both fields Use it by setting "0".
ZERO
- 20 -
CXD1910AQ
BIT Closed Caption Character #1 for 21H 7 Address 03H 6 5 4 3 2 1 0 R/W
ASCII data#1
(Default: 0H)
Closed Caption Character #2 for 21H 7 Address 04H 6 5 4 3 2 1 0 R/W
ASCII data#2
(Default: 0H)
Closed Caption Character #1 for 284H 7 Address 05H 6 5 4 3 2 1 0 R/W
ASCII data#1
(Default: 0H)
Closed Caption Character #2 for 284H 7 Address 06H 6 5 4 3 2 1 0 R/W
ASCII data#2
(Default: 0H)
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CXD1910AQ
Video Timing
YELLOW
GREEN
MAGENTA
WHITE
806
806 748 655 597 506 448 7.5 IRE 355 297
BLACK
CYAN
BLUE
RED
WHITE LEVEL
100 IRE
256 40 IRE 36
BLACK LEVEL BLANK LEVEL
SYNC LEVEL
NTSC Y (Luminance) Video Output Waveform
7.5 IRE SETUP
MAGENTA (299)
YELLOW (227)
GREEN (299)
CYAN (320)
BLUE (227)
RED (320)
832
622 20 IRE 512 402 COLOR BURST 192 BLANK LEVEL
NTSC C (Chroma) Video Output Waveform
7.5 IRE SETUP
WHITE
- 22 -
BLACK
CXD1910AQ
Video Timing
YELLOW
GREEN
MAGENTA
WHITE
806 806 744 643 580 100 IRE 482 419 318 256 40 IRE 36
BLACK
CYAN
BLUE
RED
WHITE LEVEL
BLANK LEVEL
SYNC LEVEL
NTSC Y (Luminance) Video Output Waveform No SETUP
YELLOW (245)
MAGENTA (324)
CYAN (347)
GREEN (324)
RED (347)
BLUE (245)
859
622 20 IRE 512 402 COLOR BURST BLANK LEVEL
165
NTSC C (Chroma) Video Output Waveform No SETUP
WHITE
- 23 -
BLACK
CXD1910AQ
Video Timing
YELLOW
GREEN
MAGENTA
WHITE
806
806 744 643 580 100 IRE 482 419 318
RED
BLACK
CYAN
BLUE
WHITE LEVEL
256 43 IRE 20
BLANK LEVEL
SYNC LEVEL
PAL Y (Luminance) Video Output Waveform
MAGENTA (324)
YELLOW (245)
GREEN (324)
CYAN (347)
RED (347)
BLUE (245)
WHITE
859
630 512 394
21.5 IRE BLANK LEVEL COLOR BURST
165
PAL C (Chroma) Video Output Waveform
- 24 -
BLACK
CXD1910AQ
Video Timing
YELLOW MAGENTA
GREEN
593 (81) 512
670 (158)
752 (240)
354 (-158) 272 (-240)
431 (-81)
Color Difference (U) Video Output Waveform
YELLOW
GREEN
MAGENTA
BLUE
RED
795 (283)
850 (338)
566 (54) 512 458 (-54)
229 174 (-283) (-338)
Color Difference (V) Video Output Waveform
- 25 -
BLACK
WHITE
CYAN
RED
BLUE
BLACK
WHITE
CYAN
CXD1910AQ
Internal Filter Characteristics
Interpolation Filter Characteristic
0
-10
Attenuation [dB]
-20
-30
-40
-50 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Frequency [MHz]
Chrominance Filter Characteristics
0
-20
Attenuation [dB]
-40
-60
-80
-100 0 1 2 3 4 5 6 7 8 9 10 Frequency [MHz]
- 26 -
CXD1910AQ
Application Circuit 1
CXD1910AQ
AVDD VG 0.1F VREF (1.33V) 3.3k IREF AVSS 1k
Buff AMP COMP-O Y-OUT C-OUT VB 200 LPF 75 [6dB]
Video output
0.1F
VSS
Application Circuit 2
CXD1900Q (MPEG2 decoder) CXD1910AQ (Video encoder)
8 PD0 to 7 PD0 to 7
FLDID
F-ID
HSYNC
HSYNC
VRST F1
XVRST F1
PXCLK
SYSCLK
27MHz Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXD1910AQ
Package Outline
Unit: mm
64PIN QFP(PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1
51 33
+ 0.1 0.15 - 0.05 0.15
52
32
17.9 0.4
+ 0.4 14.0 - 0.1
64
20
+ 0.2 0.1 - 0.05
1 1.0 + 0.15 0.4 - 0.1
19 + 0.35 2.75 - 0.15 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER /42 ALLOY 1.5g
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0.8 0.2
16.3

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